Knowledge Systems Laboratory, Stanford University
24
OR and AND Gates
uOR gate’s output is off when both of its inputs are off
8(=> (Type ?g OR)
8      (and (Gate ?g)
8               (<=> (Signal  (Out 1 ?g)  Off)
8                        (and   (Signal  (In 1 ?g)  Off)   (Signal  (In 2 ?g)  Off)))))
uAND gate’s output is on when both of its inputs are on
8(=> (Type ?g AND)
8      (and (Gate ?g)
8               (<=> (Signal  (Out 1 ?g)  On)
8                        (and   (Signal (In 1 ?g)  On)   (Signal  (In 2 ?g)  On)))))