OR and AND Gates
OR gate’s output is on when any of its inputs are on
(=> (Type ?g OR)
(<=> (Signal (Out 1 ?g) On)
(exists ?i (Signal (In ?i ?g) On))))
AND gate’s output is off when any of its inputs are off
(=> (Type ?g AND)
(<=> (Signal (Out 1 ?g) Off)
(exists ?i (Signal (In ?i ?g) Off))))